Synchronous type semiconductor memory devices perform read and write operations responsive to an external clock signal. One disadvantage to this type of device is the amount of time it takes for the semiconductor memory device to respond to a read address and transmit the read data stored in the cell to a data output buffer. When the period of the clock signal becomes shorter than the time for the read data to be transmitted to the data output buffer, the read data will not be output to the external device.
The pipeline method of reading data was designed to solve this problem. The pipelined method responds to the read command and outputs the read data transmitted from the memory cell to the data output buffer. From there the data is transmitted to the external device after one cycle of the read command. Unfortunately, the operational advantages of conventional pipelined read methods are limited as clock frequencies are increased. Generally, pipelined memories have a trade between clock-to-data valid times and cycle times. A number of methods have been proposed to reduce one or the other of these two times, but always at the expense of the other time. Generally, memory manufacturers can sell faster memories (clock frequency, cycle time and clock-to-data valid time) for higher prices than slower memories.
Thus there exists a need for a clocking system and method for memories that minimizes the trade between cycle time and clock-to-data valid time and allows for faster clock frequencies.